Encapsulation Technology for 3 D Stacked Packages

The continuing demand for yet smaller and lighter electronic devices requires micro packaging where shrinkage in the geometry of the substrates as well as decrease of the area of the die is needed. Higher device and circuitry integration of the silicon die, finer pitch of fully populated arrays interconnections are examples of how the industry is meeting these miniaturizations demand. Today technology however may be reaching some limitations. The concept of stacking up packages seems to be gaining popularity today as another alternative to nano-electronic packaging. The 3-dimensional (3D) assembly methods bring along several challenges in the assembly process. Small gaps, i.e., short interconnection bumps need to be encapsulated for both, reliability and performance reasons. The present paper addresses encapsulation processes for 3D like packages. It includes successful underfilling processes of Multilayer 3D like packages. Data for “best underfilling practices” of 3D stacked structures is presented. Novel encapsulation techniques leading to fast and void-free are demonstrated. Capillary flow encapsulation, along with new materials, is demonstrated to be an expeditious and robust process for 3D like electronic applications. New “Capillary Assisted” processes are revealed. Data and process parameters for these processes are assessed and benchmark against “Forced Flow Underfill Techniques.”